The invention relates to a frequency synthesizer for providing low spurous output and low electrical power consumption.
FIG. 9 is a conventional construction of a frequency synthesizer disclosed in the Japanese laid-open publication No. 63-296522 or U.S. Pat. No. 4,965,533. The basic operation of the conventional phase locked loop frequency synthesizer using the Direct Digital Frequency Synthesizer (DDS) as a reference oscillator is disclosed in the paper, Albert L. Bramble, "Direct Digital Frequency Synthesis", Digest of Proc. 35th Ann. Freq. Control Symposium, May 1981, pp406.about.414.
In FIG. 9, 1 is a direct digital synthesizer (DSS). 2 is an output terminal of the direct digital synthesizer 1. 3 is a phase comparator. 4 is a loop filter. 5 is a voltage controlled oscillator (VCO). 6 is a coupler from where the output of the synthesizer frequency is branched. 7 is a frequency divider having dividing ratio N. 8 is a phase lock loop comprised of the phase comparator 3, the loop filter 4, the voltage controlled oscillator (VCO) 5, the coupler 6 and the frequency divider 7, 9 is an output terminal of the phase lock loop 8.
An operation of the conventional frequency synthesizer shown in FIG. 9 is explained hereinafter. In the conventional frequency synthesizer, a part of the output power (frequency f.sub.0) of the VCO 5 is branched by the coupler 6. The branched frequency is divided by dividing ratio N in the frequency divider 7, and the divided frequency f.sub.0 /N is outputted to the phase comparator 3. The phase of the output signal (frequency f.sub.0 /N) from the frequency divider 7 and the output signal (frequency f.sub.d) from the direct digital synthesizer 1 are compared in the comparator 3. The output of the comparator 3 is applied to the VCO 5 through the loop filter 4 and controls the output frequency of the VCO 5. The phase lock loop 8 operates so that the frequency f.sub.0 /N from the divider 7 and the frequency f.sub.d from the direct digital synthesizer 1 becomes equal. The output frequency f.sub.0 of the frequency synthesizer is obtained in the following equation (1). EQU f.sub.0 =N.multidot.f.sub.d ( 1)
FIG. 10 illustrates one embodiment of a direct digital synthesizer (DDS). In FIG. 10, 12 is an input terminal for frequency setting data. 2 is an output terminal. 10 is a clock oscillator. 13 is a memory for digitally storing amplitude data of sine waves each having a predetermined phase. 11 is a phase accumulator for generating a phase information signal in order to read amplitude data of the sine wave stored in the memory 13 during each period of the clock signal (frequency f.sub.ck) in accordance with the frequency setting data (decimal number k). 14 is a digital to analog converter (D/A converter). 15 is a filter.
The operation of the direct digital synthesizer 1 is explained hereinafter. The output phase information signal from the phase accumulator 11 causes the memory 13 to output amplitude data of the sine waves (digital signal). The output amplitude data of the sine waves is converted into analog voltage data by the D/A converter 14. The analog data is applied to the filter 15 and undesired waves are eliminated. Assume that a word length of the phase accumulator 11 is b, then the output frequency f.sub.d of the direct digital synthesizer 1 is obtained in a equation (2). EQU f.sub.d =k.multidot.f.sub.ck /2.sup.b ( 2)
By substituting the equation (2) into the equation (1), the output frequency f.sub.0 of the frequency synthesizer is obtained in equation (3). EQU f.sub.0 =N.multidot.k.multidot.f.sub.ck /2.sup.b ( 3)
In the conventional frequency synthesizer, the output frequency f.sub.0 can be changed for each channel interval .DELTA.f.sub.0 obtained by the following equation (4) by changing the frequency setting data k. EQU .DELTA.f.sub.0 =N.multidot.f.sub.ck /2.sup.b ( 4)
In the DDS 1, the amplitude data of the sine wave are quantized and stored in the memory 13. The quantization of the signal produces a wave distortion according to the quantization roughness.
FIG. 11 illustrates an output spectrum generated in the DDS 1. In FIG. 11, the spurious signals generated by the quantization can be seen in the spectrum. If such a signal is applied to the phase lock loop 8 as a standard signal, the spurious signal is also included in the output signal of the frequency synthesizer. Assume that a spurious power ratio is S.sub.i (i=1, 2, 3, . . . ) which is the ratio of carrier signal and spurious signal at the output of the DDS 1, then a spurious power ratio S.sub.oi (i=1, 2, 3, . . . ) which is a ratio of carrier signal and spurious signal at the output of the frequency synthesizer is obtained in the following equation (5). EQU S.sub.oi =N.sup.2 .multidot..vertline.H(f.sub.m).vertline.2.multidot.S.sub.i( 5)
Where, EQU H(f.sub.m)=G(f.sub.m)/{1+G(f.sub.m)} (6) EQU G(f.sub.m)=K.sub.p .multidot.K.sub.v .multidot..vertline.F(f.sub.m)/(j2.pi.f.sub.m).vertline. (7)
f.sub.m is a offset frequency from the carrier frequency, K.sub.p is a sensitivity of the phase comparator 3, K.sub.v is a sensitivity of the VCO 5, F(f.sub.m) is a gain of the loop filter 4.
From the equation (5), it is easily understood that the output spurious signals of the frequency synthesizer decreases if a dividing ratio N of the divider 7 decreases or the absolute value of the H (f.sub.m) decreases. Since the interval between the spurious and the carrier frequency is very narrow, it is difficult to eliminate the spurious signals generated in the frequency synthesizer. It is though that the only method for solving the above problem is to decrease the dividing ratio N.
There are many methods for decreasing the dividing ratio N.
A first method is to increase the frequency of the standard signal applied to the phase comparator 3, that is, the output frequency f.sub.d of the DDS 1. But, in order to obtain a high frequency signal as an output of the DDS 1, high speed devices such as ECL (Emitter Coupled Logic) devices must be used.
FIG. 12 illustrates the characteristics between consumption power and operation frequency of ECL and CMOS being used in the DDS. The ECL devices consume a large amount of electric power rather than CMOS (Complementary Metal Oxide Semiconductor) devices as shown in FIG. 12.
As described above, in the conventional frequency synthesizer, if the frequency of the standard signal increases for eliminating the spurious signals, then the consumption power of the DDS 1 increases.
A second method is to convert the output frequency of the DDS 5 to a higher frequency using converter means, instead of increasing the frequency of the DDS 5. The converted frequency signal is used as a standard signal and applied to the phase comparator 3.
FIG. 13 illustrates a conventional frequency synthesizer including a phase locked loop as a multiplier used for such conversion means described in the laid-open patent publication No. 64-24633/1989. In FIG. 13, 1a and 1b are direct digital synthesizers (DDS). 8 is a phase lock loop having the same function as that in FIG. 6. 18 is a filter. 26 is a multiplier using phase lock loop. 16 is a mixer for mixing the branched output of the frequency synthesizer and the output of the multiplier 26. 19 is a frequency converter comprised of the DDS 1b, the multiplier 26, the mixer 16 and the filter 18.
In FIG. 13, an output frequency of the DDS 1b is multiplied by the multiplier 26 having a phase lock loop in it. The output of the multiplier 26 is outputted to the mixer 16 and is mixed with the output of the VCO 5 (frequency f.sub.0) to obtain a difference signal. A resultant output signal from the mixer 16 is applied to the filter 18 for eliminating the spurious signals. The output signal from the filter 18 is applied to the phase comparator 3 with the output from the DDS 1a to obtain a constant output frequency f.sub.0 from the output terminal 9.
In the above construction, since the spurious signal at the output of the frequency converter 19 increases in proportion to the square of the multiplication number N of the multiplier 26 as shown in the equation (5), the output signal is almost the same as S.sub.oi in the frequency synthesizer of FIG. 9. Therefore, even if the dividing ratio of the phase lock loop, including the phase comparator 3, loop filter 4 and VCO 5, is equal to 1, the spurious signal at the output terminal 9 is not eliminated. That is, the frequency synthesizer shown in FIG. 13 is suitable for generating a comparatively low frequency signal for a narrow frequency interval, but it is not suitable for eliminating the spurious signal.
It is a primary object of the present invention to provide a frequency synthesizer having low spurious signal and low power consumption.